Changes in reSID version 1.0
----------------------------

*** NB! This is a pre-release, for testing only. ***

This release of reSID brings SID emulation to the next level.

The complete known digital state machine is emulated with full cycle
accuracy, and the emulation of the SID 6581 filter is, for the first
time, getting quite close to a real SID chip.

This release would not have been possible without the work of Michael
Huth, who has made high quality SID die photographs available, and
Tommi Lempinen, who has done impressive work revectorizing and
annotating these die photographs.

The revectorized die photographs have made it possible to model the
SID filter and audio output stage topology at the transistor level. A
DAQ has been used to sample the SID capacitor pins in order to work
out an op-amp transfer function, and furthermore transistor currents
and thus transistor parameters.

The revectorized die photographs have also been used to work out
correct models for the noise waveform shift register and for the MOS
6581 non-monotonic D/A converters.

Honorable mention must also go to Otto Jarvinen, for his important
contributions to understanding of the SID chip and thus emulation
quality (test bit behavior, waveform 0 behavior), and to Antti
Lankila, for tirelessly working to improve SID emulation.

The improvements to emulation are summarized as follows:

* Data bus
  - MOS 8580 one-cycle pipeline write delay
* Waveform generator
  - Shift register
    - corrected output and feedback topology
    - effects of the test bit
    - two-cycle pipeline delay (only for single-cycle clocking)
    - writes by combined waveforms
  - Pulse waveform one-cycle pipeline delay (only for single-cycle
    clocking)
  - Emulation of floating waveform DAC input for waveform 0
  - Accurate model of non-monotonic MOS 6581 D/A converter
* Envelope generator
  - Exponential frequency divider one-cycle pipeline delay (only for
    single-cycle clocking)
  - Accurate model of non-monotonic MOS 6581 D/A converter
* Filter and audio output stage
  - Accurate model of complete topology for the MOS 6581
  - Accurate model of the MOS 6581 op-amps
  - Accurate model of gain/summer op-amp transistor inputs and feedbacks
  - Accurate model of integrator op-amp VCR inputs
  - Accurate model of non-monotonic MOS 6581 D/A converter
* External filter
  - Improved resolution

Some other improvements are:

* The SID interface is enclosed in the namespace "reSID" to avoid name
  clashes with other libraries.
* Architecture specific optimizations, including vectorization, are
  available via the default configure option --enable-arch=native.
* Branch prediction hints are included via the default configure
  option --enable-branch-hints.
* Fixed a bug in resampling FIR table wraparound, courtesy of Antti
  Lankila.
* Novel near branch-free calculation of waveform outputs, inspired by
  Antti Lankilas resid-fp fork.
* Voice muting is available for test purposes.

Enjoy!

Dag Lem


Changes in reSID version 0.16
-----------------------------

An off-by-one error in the emulation of the ADSR delay bug has been
fixed in the fast version of the envelope clocking.

An initialization bug in the Filter class which caused floating point
exceptions on some platforms has been fixed.

Missing fields have been added to SID::State for correct snapshots.

By building shifted FIR tables with samples according to the sampling
frequency, the resampling code dramatically reduces the computational
effort in the filter convolutions, without any loss of accuracy. The
filter convolutions are now also vectorizable on current hardware. The
implementation builds on ideas by Laurent Ganier.

The resampling code has been split into two functions, one using
interpolation and a small set of shifted filter tables, and one using
direct lookup and a large set of shifted filter tables. The accuracy
is the same, the difference is that the direct lookup runs has the
potential of running at almost twice the speed (depending on cache
size and memory bandwidth) using approximately 16MB more memory. It is
now possible to run high quality resampling in real time on quite
modest hardware, provided that a vectorizing compiler is used.


Changes in reSID version 0.15
-----------------------------

An error in the emulation of the ADSR delay bug has been fixed. When
emulation of the ADSR delay bug was introduced in reSID 0.2, the delay
was one cycle too long. One cycle was subtracted from the delay in
reSID 0.4, however unfortunately one rate counter period was added as
well, thus increasing the error. At the time there was no method to
fully synchronize the CPU with envelope 3, so the measurements relied
on averaging. Because of pipelining in the envelope logic the effects
of a write are delayed, and this caused the test code to miss the
target by exactly one rate counter period on a real SID. The current
test code does achieve full synchronization with envelope 3, so this
time the delay should be 100% correct. There are still side effects
caused by pipelining which are not implemented in reSID, however these
effects are not controllable without full synchronization with the
envelope, something which is hard to achieve with envelope 3, and
impossible with envelope 1 and 2.

The envelope state (ADSR) has been added to the SID state, and the
volume setting is now restored from the SID state.

Filter scaling and clipping has been added to avoid sample overflows
in the resampling filter.


Changes in reSID version 0.14
-----------------------------

The SID external audio input is now emulated. This can be used e.g. to
simulate the hack of connecting a resistor from EXT IN to GND to boost
the sample volume on the MOS8580. Calling sid.input(-32768) makes the
MOS8580 sound more or less like the MOS6581 with respect to samples.
The interface could also be used to mix in an external audio signal,
but note that to do this correctly you should really resample the
audio signal to 1MHz first.

The filter settings are now updated immediately when the chip model is
changed. Earlier the filter cutoff frequency would not change until
the FC registers were updated.

A one cycle error in the fast version of the envelope clocking has
been fixed. This bug was introduced in reSID 0.13 and could affect the
ADSR delay emulation.

The exponential counter period is now only loaded at the envelope
counter values 255, 93, 54, 26, 14, 6, 0. The period can be different
for the same envelope counter value, depending on whether the envelope
has been rising (attack -> release) or sinking (decay/release).

A bug in the fast version of the noise register shift routine has been
corrected. This bug caused too low noise frequency in some cases.

The filter cutoff frequency is limited to 16kHz to keep the filter stable.


Changes in reSID version 0.13
-----------------------------

The internal DC levels of the MOS6581 have been double checked and
corrected. The reason for the asymmetric scaling of the voice output
has been found; there is a DC offset from the waveform D/A converter
in addition to the DC offset from the envelope multiplying D/A
converter. No selected waveform (N=P=S=T=0) yields minimum wave output
level again.

A bug in the fast version of the envelope clocking has been corrected.
This bug could incorrectly invoke the ADSR delay emulation.


Changes in reSID version 0.12
-----------------------------

A bug causing incorrect sample spacing in the new SAMPLE_FAST sample
calculation has been corrected.

Audio clipping has been added to guard against sample overflows.

To support multi-channel sampling, sample interleaving has been added
to the clock() interface.

To support synchronization with an external timer, an interface for
sample rate adjustment has been added.

The internal DC levels have been corrected. No selected waveform
(N=P=S=T=0) yields maximum wave output level. Furthermore, each voice
in the MOS6581 independently contributes to the DC level in the mixer,
and the mixer itself has a small DC offset as well. The MOS8580 has no
DC offsets.

The spline interpolation routine has been generalized to accept
repeated points to introduce points of non-differentiability and
discontinuity.

A separate mapping from the FC registers to filter cutoff frequency
has been included for the MOS8580, and the mapping for the MOS6581 has
been refined.


Changes in reSID version 0.11
-----------------------------

A new clock() interface has been added. This function generates audio
samples into a buffer, greatly simplifying the task of writing driver
code for reSID. It also facilitates more advanced audio sample
generation, as described below.

Three clocking methods are available: clocking at output sample
frequency, clocking at cycle frequency with linear sample
interpolation, and clocking at cycle frequency with audio resampling.

Clocking at output sample frequency is fast, and yields acceptable
sound quality, except for the SID combined waveforms, which have a
very high frequency content.

Clocking at cycle frequency with linear sample interpolation is
approximately five to ten times slower at 44.1kHz sampling frequency,
but the sound quality is improved because of the linear sample
interpolation, and because some sampling noise is removed by the SID
external filter, which attenuates signals above 16kHz.

Finally, clocking at cycle frequency with audio resampling has a work
rate which is independent of the sampling frequency; it is rather
inversely proportional to the percentage of the bandwidth allocated
to the filter transition band. This implies that e.g. with the
transition band starting at ~ 20kHz, it is faster to generate 48kHz
than 44.1kHz samples.

Audio resampling is the theoretically correct method for sample
generation, and delivers SID sound quality previously unheard of. This
should make connoisseurs nod in appreciation, and for some time to
come it could possibly also make people tear their hair over having to
buy state of the art hardware to handle the obscene workload in real
time. By trading off passband bandwidth for speed, real time
processing is possible on current hardware. A 60% passband bandwidth
is within the reach of reasonably fast machines, while maximum sound
quality at 90% passband bandwidth, requiring four times the processing
power, is not. Yet.


Changes in reSID version 0.10
-----------------------------

Libtool is now used to build the library.

To keep the filters stable it is necessary to clock them at above
sample rate. The chip clocking code has been modified to only
"overclock" the filters, not the whole chip. This yields a
considerable speedup without noticeably lowering sound quality. Note
that this is aimed at slow hardware, if possible the 1 cycle clock
interface should be used to eliminate sampling noise.


Changes in reSID version 0.9
----------------------------

The sum of the filter outputs is no longer weighted.


Changes in reSID version 0.8
----------------------------

voice3off has no effect if voice 3 is routed through the filter.


Changes in reSID version 0.7
----------------------------

The audio output filter in the C64, external to the SID chip, has been
modeled.

The mapping function between the FC register and filter cutoff frequency can
now be specified with spline interpolation points. This facilitates
interactive modification of the mapping function by graphical presentation of
the interpolation curve. The implementation of this novel spline design is
fast and general purpose, and should be well suited for use in other projects
as well.

Filtered output has been inverted compared to unfiltered output.

Aging of the bus value obtained when reading write only registers has been
partly implemented.

To facilitate offline storage the complete state of SID can be read and
written.


Changes in reSID version 0.6
----------------------------

A special case in synchronization has been implemented.

The Autoconf script is cleaned up to allow compilation in a separate directory.


Changes in reSID version 0.5
----------------------------

Emulation of MOS8580 combined waveforms.

Version string resid_version_string provided for e.g. Autoconf tests.
The string has C linkage.


Changes in reSID version 0.4
----------------------------

The implementation of the ADSR delay bug has been refined and should now be
cycle exact.

The patch for VICE has been removed since VICE 0.15 will include reSID support.


Changes in reSID version 0.3
----------------------------

The reSID library has changed name from libmos6581.a to libresid.a

The pulse+sawtooth combined waveform has been corrected.

Pulse+test bit samples are implemented.

The envelope rate periods have finally been exactly determined.

A new SID bug, the ADSR boundary bug, has been discovered and implemented.
This bug makes it possible to step from envelope level 0x00 to 0xff or from
0xff to 0x00 in one step.

One-cycle optimized overloads of the clock() functions have been implemented
to facilitate sampling at 1MHz.

The code has been further optimized for speed.


Changes in reSID version 0.2
----------------------------

The implementation of the Envelope Generator has been rewritten to handle
the infamous ADSR delay bug. All known envelope related bugs have been
corrected.

The maximum filter resonance is lowered to keep the filter stable.

The reSID API has been simplified. Reading write only registers is allowed.
